An electrically erasable programmable read only memory (EEPROM) device is a non-volatile memory device in which data can be electrically programmed and erased therein. A floating gate tunnel oxide (FLOTOX) EEPROM stores data at logic levels of a “1” or “0” by injecting electrons into or discharging electrons from a floating gate insulated from a peripheral area, using the Fowler-Nordheim effect.
In a memory cell of an EEPROM, the size of a unit cell is reduced as the capacity of cell memory increases. However, when the size of a unit cell is reduced, cell characteristics can be degraded. For example, an inconsistency in cell threshold voltages Vth of the erased cells and the programmed cells may occur. A reason of the inconsistency of the cell threshold voltages Vth is a shortened effective channel length of a memory transistor. By increasing the effective channel length without increasing the size of the cells, the cell threshold voltage distribution can be improved.
FIG. 1A is a layout of a conventional FLOTOX EEPROM cell. FIGS. 1B and 1C are cross-sectional views taken along lines Y–Y′ and X–X′ in FIG. 1, respectively.
Referring to FIGS. 1A to 1C, a memory cell of an EEPROM is formed along an active region 103, in which two transistors are formed in series. The active region 103 is separated by an inactive region formed of a field insulating film 105. One of the two transistors is a memory transistor including a floating gate 141 and is electrically connected to a sense line 143. The other transistor is a select transistor electrically connected to a word line 145. A drain region of the select transistor electrically connected to a bit line (not shown) constitutes a bit line junction region 139. A source region of the select transistor and a drain region of the memory transistor constitute a floating junction region 130. A source region of the memory transistor constitutes a common source region 138.
Referring to FIG. 1C, a gate insulating layer 116a including a thin tunnel insulating film 114 is formed on a portion of the floating junction region 130. A memory transistor gate includes a floating gate 141, an inter-gate insulating film 142, and a control gate 143, stacked on the gate insulating film 116a. The control gate 143 forms a sense line extending along a line. A select transistor gate 145 formed on a gate insulating film 116b is separated at a distance from the memory transistor. The select transistor gate 145 forms a word line that extends along a line. Side wall spacers 115 are formed on side walls of the memory transistor gate (including 141, 142, and 143) and the select transistor gate 145.
The floating junction region 130 extends to a side of the select transistor gate 145 and is formed below the tunnel insulating film 114. The floating junction region 130 includes a deep N+ type dopant region 131 below the tunnel insulating film 114 and a high voltage N− (HVN−) type dopant region 132 formed adjacent to the deep N+ type dopant region. The HVN− indicates an N− type dopant suitable for an application of a high voltage of about 15V˜about 20V. The HVN− has a greater junction depth than an N+ type dopant region 135.
The common source region 138 has a double diffusion (DD) structure. In other words, the N+ type dopant region 135 is formed on the HVN− dopant region 134. The bit line junction region 139 also has a double diffusion structure with the N+ type dopant region 136 formed on the HVN− region 133. The HVN− type dopant regions 132, 133, and 134 have greater junction depths than the N+ type dopant regions 135 and 136.
In a conventional EEPROM, the HVN− dopant regions 132, 133, and 134 are formed to equal depths on the substrate 100 after the deep N+ type dopant region 131 of the floating junction region 130 is formed. Then, the common source region 138 including a double diffusion structure is formed by the N+ type dopant region 135 in the common source region 138. The bit line junction region 139 including the double diffusion structure is formed by the N+ type dopant region 136 in the bit line junction region 139. The N+ type dopant regions 135 and 136 have shallower depths than the HVN− type dopant regions 132, 133, and 134.
In the conventional EEPROM cell, the HVN− dopant region 134 in the common source region 138 is formed at the same time and to the same depth as the HVN− dopant regions 132 and 133. As a result, lateral diffusion toward the floating junction region 130 becomes large. Accordingly, an effective channel length of the memory transistor reduces to the extent of the lateral diffusion. A reduced effective channel length may result in an uneven distribution of a threshold voltage.
FIG. 1D is a cross-sectional view of another conventional EEPROM. Referring to FIG. 1D, the common source region 138 has a lightly doped drain (LDD) structure. Japanese Patent Laid-Open Publication No. 2002-305260 discloses an EEPROM cell including a common source region with the LDD structure.
In EEPROM structure of FIG. 1D, the common source region 138 includes the LDD structure by forming a low voltage N− LVN− dopant region with a shallow depth between the N+ type dopant region 135 and the channel. As a result, the LVN− type dopant region 137 is formed with a shallower depth than the HVN− type dopant regions 132 and 133. As the extent of lateral diffusion decreases, the effective channel length of the transistor increases. Decreased lateral diffusion reduces inconsistencies in the threshold voltage.